Typical prior art approaches to determining bit integrity to a circuit, such as an elastic buffer, included using another elastic buffer in parallel with the elastic buffer in the path to be tested, and sending data through both identical elastic buffer paths and comparing the output of both paths. Such an approach is shown in U.S. Pat. No. 4,601,028 in the name of Huffman et al. and assigned to the same assignee as the present invention. The disadvantage to such an approach is the amount of logic and circuitry required to test the data path. By eliminating the need for a second elastic buffer, this invention requires less circuitry and, therefore, less cost, greater reliability and smaller physical size.
Another common prior art approach for accurately determining the time delay of data through a circuit being tested, is to use a phase-locked loop to coordinate the clocks at the input and output circuitry, thus eliminating the need for an elastic buffer. It is not always practical to perform such a phase lock approach, and thus elastic buffers are required.
The environment for the circuitry to be checked, in one embodiment of the inventive concept, concerns a situation where the data transmission rate is greater than one megabit per second of information being transmitted. If a circuit is checked even as little as 10% of the time, it is still checked many times per second. Thus, if data input to a circuit is sampled and held in a given register, and then data being output from this same circuit is compared with that held in the input register, and the comparison is checked for each clock subsequent thereto for a number of clocks equal to the maximum possible time delay in the circuit, a definite determination can be made as to whether or not the data is passing through the circuit correctly. Although there is certainly a possibility that the detected comparison will be to a set of data identical in logic value to, but different from the data actually input, the statistical probability is that this will only occur a very small percentage of the time. When the checking occurs at a rate of many times per second, the determination of problems will still be correctly reported very quickly. If an error is indicated, the circuitry involved switches the transmission of data to another channel. During this switching operation, even though it may take a matter of milliseconds, there is a considerable loss of data. Thus, it is undesirable to switch channels unless there really is a problem.
The present concept is thus based upon the realization that occasional "false" indications of correct compares is OK when a large number of compares are being performed as long as an error signal indicating a "bad" compare is always correct.